AO4292 general description product summary v ds i d (at v gs =10v) 8a r ds(on) (at v gs =10v) < 23m r ds(on) (at v gs =4.5v) < 33m applications 100% uis tested 100% rg tested symbol v 100v n-channel alphamos orderable part number package type form minimum order quantity 100v ? trench power alphamos ( mos mv) technology ? low r ds(on) ? low gate charge ? optimized for fast-switching applications ? rohs and halogen-free compliant absolute maximum ratings t a =25c unless otherwise noted v maximum units AO4292 so-8 tape & reel 3000 ? synchronus rectification in dc/dc and ac/dc conve rters ? isolated dc/dc converters in telecom and industri al 100 parameter drain-source voltage g ds soic-8 top view bottom view d d d d s s s g v ds v gs i dm i as avalanche energy l=0.1mh c e as v ds spike v spike t j , t stg symbol t 10s steady-state steady-state r q jl t a =25c t a =70c t a =25c avalanche current c thermal characteristics w i d v a 15 32 mj 11 8 parameter max c units junction and storage temperature range -55 to 150 typ maximum junction-to-ambient a c/w r q ja 31 59 40 va 20 v maximum junction-to-lead c/w c/w maximum junction-to-ambient a d 16 75 24 power dissipation b 2.0 t a =70c 10 s p d 100 120 3.1 gate-source voltage pulsed drain current c 6.2 drain-source voltage continuous drain current rev.1.0: january 2014 www.aosmd.com page 1 of 5
symbol min typ max units bv dss 100 v v ds =100v, v gs =0v 1 t j =55c 5 i gss 100 na v gs(th) gate threshold voltage 1.6 2.15 2.7 v 18 23 t j =125c 32.5 42 24 33 m g fs 30 s v sd 0.72 1 v i s 4 a c iss 1190 pf c oss 95 pf c rss 7 pf r g 0.5 1.1 1.7 q g (10v) 16.5 25 nc q g (4.5v) 7 12 nc q gs 4.5 nc q gd 2.5 nc t d(on) 7 ns t r 3 ns t d(off) 20 ns t f 3 ns m v gs =10v, v ds =50v, i d =8a total gate charge electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions gate resistance f=1mhz i dss a zero gate voltage drain current drain-source breakdown voltage i d =250 m a, v gs =0v r ds(on) static drain-source on-resistance gate source charge gate drain charge total gate charge switching parameters turn-on delaytime v ds =0v, v gs =20v maximum body-diode continuous current input capacitance gate-body leakage current turn-off delaytime turn-off fall time v gs =10v, v ds =50v, r l =6.25 w , r gen =3 w diode forward voltage dynamic parameters v gs =4.5v, i d =6a turn-on rise time reverse transfer capacitance v gs =0v, v ds =50v, f=1mhz v ds =v gs, i d =250 m a output capacitance forward transconductance i s =1a,v gs =0v v ds =5v, i d =8a v gs =10v, i d =8a t f 3 ns t rr 20 ns q rr 90 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. body diode reverse recovery charge body diode reverse recovery time i f =8a, di/dt=500a/ m s turn-off fall time i f =8a, di/dt=500a/ m s a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air environ ment with t a =25 c. the value in any given application depends on the user' s specific board design. b. the power dissipation p d is based on t j(max) =150 c, using 10s junction-to-ambient thermal resistance. c. repetitive rating, pulse width limited by junct ion temperature t j(max) =150 c. ratings are based on low frequency and duty cycl es to keep initialt j =25 c. d. the r q ja is the sum of the thermal impedance from junction t o lead r q jl and lead to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-ambien t thermal impedance which is measured with the devi ce mounted on 1in 2 fr-4 board with 2oz. copper, assuming a maximum junction temperatur e of t j(max) =150 c. the soa curve provides a single pulse rating. rev.1.0: january 2014 www.aosmd.com page 2 of 5
typical electrical and thermal characteristics 0 10 20 30 40 1 2 3 4 5 i d (a) v gs (volts) figure 2: transfer characteristics (note e) 10 15 20 25 30 0 5 10 15 20 r ds(on) (m w ww w ) i d (a) figure 3: on - resistance vs. drain current and gate 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0 25 50 75 100 125 150 175 normalized on-resistance temperature (c) figure 4: on - resistance vs. junction temperature v gs =4.5v i d =6a v gs =10v i d =8a 25 c 125 c v ds =5v v gs =4.5v v gs =10v 0 10 20 30 40 0 1 2 3 4 5 i d (a) v ds (volts) figure 1: on-region characteristics (note e) v gs =3v 3.5v 4.5v 10v 4v d figure 3: on - resistance vs. drain current and gate voltage (note e) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.0 0.2 0.4 0.6 0.8 1.0 i s (a) v sd (volts) figure 6: body-diode characteristics (note e) 25 c 125 c figure 4: on - resistance vs. junction temperature (note e) 10 20 30 40 50 60 2 4 6 8 10 r ds(on) (m w ww w ) v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) i d =8a 25 c 125 c rev.1.0: january 2014 www.aosmd.com page 3 of 5
typical electrical and thermal characteristics 0 2 4 6 8 10 0 4 8 12 16 20 v gs (volts) q g (nc) figure 7: gate-charge characteristics 0 200 400 600 800 1000 1200 1400 1600 0 20 40 60 80 100 capacitance (pf) v ds (volts) figure 8: capacitance characteristics c iss 1 10 100 1000 1e-05 0.001 0.1 10 power (w) pulse width (s) c oss c rss v ds =50v i d =8a t j(max) =150 c t a =25 c 10 m s 0.0 0.1 1.0 10.0 100.0 0.01 0.1 1 10 100 1000 i d (amps) v ds (volts) v > or equal to 4.5v 10 m s 1ms dc r ds(on) limited t j(max) =150 c t a =25 c 100 m s 10ms pulse width (s) figure 10: single pulse power rating junction-to- ambient (note f) 0.001 0.01 0.1 1 10 1e-05 0.0001 0.001 0.01 0.1 1 10 100 z q qq q ja normalized transient thermal resistance pulse width (s) figure 11: normalized maximum transient thermal imp edance (note f) single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse v gs > or equal to 4.5v figure 9: maximum forward biased safe operating area (note f) r q ja =75 c/w rev.1.0: january 2014 www.aosmd.com page 4 of 5
- + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off l unclamped inductive switching (uis) test circuit & waveforms vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev.1.0: january 2014 www.aosmd.com page 5 of 5
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